1. Technical Field
The present invention relates to a test apparatus and a test module. In particular, the present invention relates to a test apparatus and a test module provided with a plurality of variable delay circuits.
2. Related Art
A test apparatus such as a memory tester delays a reference clock using variable delay circuits to generate timing signals indicating certain edge timings, and then generates test signals that are supplied to a device under test according to the timing signals. The variable delay circuits change the delay amount of the reference clock according to the times designated by the test patterns.
Here, the variable delay circuits aim to accurately control the delay amount, and therefore can change the delay amount by time increments that are sufficiently shorter than the resolution of the time designated by the test patterns, as shown in, for example, Japanese Patent Application Publication No. 2006-54731. Accordingly, before testing, the test apparatus must perform a process, such as a linearity correction process, that measures the actual delay time of the delay setting for each of the variable delay circuits and stores each time designated by the test pattern in the memory, e.g. a linearized memory, along with the setting value of the corresponding variable delay circuit.
The test apparatus sequentially selects one variable delay circuit at a time to undergo the linearity correction process using one main control apparatus, such as a system controller. Furthermore, test apparatuses are being provided with more variable delay circuits to enable parallel testing of a greater number of pins. Therefore, it is difficult for conventional test apparatuses to perform the linearity correction process before testing in a short amount of time.